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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16835A
MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT
DESCRIPTION
The PD16835A is a monolithic quad H bridge driver IC that employs a CMOS control circuit and a MOS FET output circuit. Because it uses MOS FETs in its output stage, this driver IC consumes less power than conventional driver ICs that use bipolar transistors. Because the PD16835A controls a motor by inputting serial data, its package has been shrunk and the number of pins reduced. As a result, the performance of the application set can be improved and the size of the set has been reduced. The PD16835A employs a current-controlled 64-step micro step driving method that drives stepper motor with low vibration. The PD16835A is housed in a 38-pin plastic shrink SOP to contribute to the miniaturization of the application set. The PD16835A can simultaneously drive two stepper motors and is ideal for the mechanisms of camcorders.
FEATURES
* Four H bridge circuits employing power MOS FETs * Current-controlled 64-step micro step driving * Motor control by serial data (8 bytes x 8 bits) (original oscillation: 4-MHz input) Data is input with the LSB first. EVR reference setting voltage: 100 to 250 mV (@VREF = 250 mV) ... 4-bit data input (10-mV step) Chopping frequency: 32 to 124 kHz ... 5-bit data input (4-kHz step) Original oscillation division or internal oscillation selectable Number of pulses in 1 VD: 0 to 252 pulses ... 6 bits + 2-bit data input (4 pulses/step) Step cycle: 0.25 to 8191.75 s ... 15-bit data input (0.25- s step) * 3-V power supply. Minimum operating voltage: 2.7 V (MIN.) * Low current consumption IDD: 3.0 mA (MAX.), IDD (RESET): 100 A (MAX.), IMO(RESET): 1.0 A (MAX.) * 38-pin plastic shrink SOP (7.62 mm (300))
ORDERING INFORMATION
Part number Package 38-pin plastic shrink SOP (7.62 mm (300))
PD16835AGS-BGG
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S15973EJ1V0DS00 (1st edition) Date Published February 2002 N CP(K) Printed in Japan
(c)
2002
2
OSCIN 37 RESET VDD VM1 VM2 VM3
Data Sheet S15973EJ1V0DS
BLOCK DIAGRAM
OSCOUT 36
VD 32
VREF 7
SCLK 35
SDATA 34
LATCH 33
EXP0 EXP1 EXP2 EXP3 17 18 19 21
38 8 23 SERIAL-PARARELLE DECODER 27 9 1/N 13 EVR1 EVR2 EVR1 EVR2 22 31 2 EXT EXT PULSE GENERATER EXTOUT SELECTOR x2
VM4
COSC
SELECTOR
OSC
CURRENT SET
CURRENT SET
+ + - VM LGND 1 + FILTER VM - + FILTER VM - + + FILTER VM - +
+
FILTER
PGND
20
H BRIDGE 1ch
H BRIDGE 2ch
H BRIDGE 1ch
H BRIDGE 2ch
25 FBA A1
24 A2
26
3 FBB
29 B1
28 B2
30
4 FBC
15 C1
16 C2
14
5 FBD
11 D1
12 D2
10
6
FILA
FILB
FILC
FILD
PD16835A
PD16835A
PIN CONFIGURATION
38-pin plastic shrink SOP (7.62 mm (300))
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 LGND COSC FILA FILB FILC FILD VREF VDD VM3 D2 FBD D1 VM4 C2 FBC C1 EXP0 EXP1 EXP2 RESET OSCOUT OSCIN SCLK SDATA LATCH VD EXT B2 FBB B1 VM2 A2 FBA A1 VM1 EXT EXP3 PGND 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20
Data Sheet S15973EJ1V0DS
3
PD16835A
1. PIN FUNCTIONS
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Symbol LGND COSC FILA FILB FILC FILD VREF VDD VM3 D2 FBD D1 VM4 C2 FBC C1 EXP0 EXP1 EXP2 PGND EXP3 EXT VM1 A1 FBA A2 VM2 B1 FBB B2 EXT VD LATCH SDATA SCLK OSCIN OSCOUT RESET Control circuit GND pin Chopping capacitor connection pin Function
1-ch filter capacitor connection pin (1000 pF TYP.) 2-ch filter capacitor connection pin (1000 pF TYP.) 1-ch filter capacitor connection pin (1000 pF TYP.) 2-ch filter capacitor connection pin (1000 pF TYP.)
Reference voltage input pin (250 mV TYP.) Control circuit supply voltage input pin Output circuit supply voltage input pin
2-ch output pin 2-ch sense resistor connection pin 2-ch output pin
Output circuit supply voltage connection pin
1-ch output pin 1-ch sense resistor connection pin 1-ch output pin
Output monitor pin (open drain) Output monitor pin (open drain) Output monitor pin (open drain) Power circuit GND pin Output monitor pin (open drain) Logic circuit monitor pin Output circuit supply voltage input pin
1-ch output pin 1-ch sense resistor connection pin 1-ch output pin
Output circuit supply voltage input pin
2-ch output pin 2-ch sense resistor connection pin 2-ch output pin
Logic circuit monitor pin Video sync signal input pin Latch signal input pin Serial data input pin Serial clock input pin Original oscillation input pin (4 MHz TYP.) Original oscillation output pin Reset signal output pin
4
Data Sheet S15973EJ1V0DS
PD16835A
2. I/O PIN EQUIVALENT CIRCUIT
Pin Name Equivalent Circuit Pin Name Equivalent Circuit
VDD
VDD
VDD LATCH SDATA SCLK
Pad Pull-down resistor (125 )
OSCIN RESET
Pad
VDD
VDD
OSCOUT EXT EXT
Pad
EXP0 EXP1 EXP2 EXP3
Pad
VDD
VDD
VREF
Pad
FILA FILB FILC FILD
Pad Buffer
VM
A1, A2 B1, B2 C1, C2 D1, D2
Parasitic diodes
Pad
FB
Data Sheet S15973EJ1V0DS
5
6
CPU 250 mV EVR : 1010 fOSC : 64 kHz 100 k x 4 OSCOUT VD VREF SCLK SDATA LATCH EXP0 EXP1 EXP2 EXP3 4 MHz OSCIN RESET REGULATOR 3.3 V VDD VM1 VM2 VM3 1/N VM4 EVR1 EVR2 COSC BATTERY 4.8 to 11 V 33 pF
+ + - + + +
3. EXAMPLE OF STANDARD CONNECTION
x2 SERIAL-PARARELLE DECODER PULSE GENERATER EVR1 EVR2 CURRENT SET EXTOUT SELECTOR
Data Sheet S15973EJ1V0DS
SELECTOR
OSC
CURRENT SET
EXT EXT
FILTER VM
-
+
FILTER VM
-
+
FILTER VM
-
+
FILTER
VM LGND PGND H BRIDGE 1ch
H BRIDGE 2ch
H BRIDGE 1ch
H BRIDGE 2ch
FBA 6.8 x 2
A1
A2 FILA FBB
B1
B2 FILB
FBC
C1
C2 FILC FBD
D1
D2 FILD 1000 pF
6.8
6.8 1000 pF
1000 pF x 2 MOTOR 1 MOTOR 2
PD16835A
PD16835A
4. STANDARD CHARACTERISTICS CURVES
PT vs. TA Characteristics
1.4
OFF VM pin Current IMO (RESET) ( A)
IMO (RESET) vs. VM Characteristics
1 TA = 25C, no load, after reset
1.2
Total Power Dissipation PT (W)
0.8
1.0 125C/W 0.8 0.6 0.4 0.2 0 -10
0.6
0.4
0.2
0
80 100 20 40 60 Ambient Temperature TA (C)
120
0
4
6 8 10 Output Circuit Supply Voltage VM (V)
12
IDD vs. VDD Characteristics
5
VDD pin Current at Reset State IDD (RESET) (A)
IDD (RESET) vs. VDD Characteristics
200 TA = 25C, after reset 150
TA = 25C, operating, 4
VDD pin Current IDD (mA)
output open
3
100
2
50
1
0
2
3 4 5 Control Circuit Supply Volage VDD (V)
6
0
2
3 4 5 Control Circuit Supply Volage VDD (V)
6
VIH/VDD, VIL/VDD vs. VDD Characteristics
1 TA = 25C
Input Voltage VIH/VDD, VIL/VDD (V) High-level/Low-level Input Current IIH/IIL ( A)
IIH/IIL vs. VIN Characteristics
60 TA = 25C, IIH: VIN = VDD, IIL: VIN = 0 V 40 IIH
0.8
0.6
VIH VIL
0.4
20
0.2
0 2 3
IIL 5 4 Input Voltage VIN (V) 6
0
2
3 4 5 Control Circuit Supply Volage VDD (V)
6
Data Sheet S15973EJ1V0DS
7
PD16835A
fOSC vs. VDD Characteristics
150 TA = 25C, COSC = 100 pF, DATA: all high 6 TA = 25C, COSC = 100 pF
fSTEP vs. VDD Characteristics
Chopping Frequency fOSC (kHz)
140
Step Frequency fSTEP (kHz)
2 3 4 5 Control Circuit Supply Voltage VDD (V) 6
5
130
120
4
110
3
100
90
2
2
3 4 5 Control Circuit Supply Voltage VDD (V)
6
VREFVER vs. VDD Characteristics
40 80
IM (MAX) vs. EVR Characteristics
Sine Wave Peak Output Current IM (MAX) (mA)
TA = 25C, VM = 6 V Rs = 6.8 , fOSC = 64 kHz, L = 25 mH/R = 100 at 1 kHz
TA = 25C, VREF = 250 mV
EVR Variable Voltage VREFVER (mV)
70
30
60
20
50
40
10
30
0
2
5 3 4 Control Circuit Supply Voltage VDD (V)
6
20 50
100 150 200 250 Reference Setting Voltage EVR (mV)
300
tON, tOFF vs. VM Characteristics
500
Turn-on Time, Turn-off Time tON/tOFF (ns)
400
TA = 25C, IM = 100 mA, CFIL : none
300
tON tOFF
200
100
0
4
10 6 8 Output Circuit Supply Voltage VM (V)
12
8
Data Sheet S15973EJ1V0DS
PD16835A
5. INTERFACE (I/F) CIRCUIT DATA CONFIGURATION (fCLK = 4-MHz EXTERNAL CLOCK INPUT)
Input data consists of serial data (8 bytes x 8 bits). Input serial data with the LSB first, from the 1st byte to 8th byte. (1) Initial data <1st byte>
Bit D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 0 1 or 0 1 or 0 1 or 0 1 or 0 EXP3 EXP2 EXP1 EXP0 Data Function
HEADER DATA2 HEADER DATA1 HEADER DATA0
(2) Standard data <1st byte>
Setting DATA selection Bit D7 D6 D5 - Hi-Z or L Hi-Z or L Hi-Z or L Hi-Z or L D4 D3 D2 D1 D0 0 0 0 0 1 or 0 1 or 0 1 or 0 1 or 0 EXP3 EXP2 EXP1 EXP0 Data Function
HEADER DATA2 HEADER DATA1 HEADER DATA0
Setting DATA selection
-
-
- Hi-Z or L Hi-Z or L Hi-Z or L Hi-Z or L
Remark Hi-Z : High impedance, L : Low level (current sink) <2nd byte>
Bit D7 D6 D5 D4 D3 D2 D1 D0 8-bit data input Note First Point Wait Start point wait
256 s to 65.28 ms
Remark Hi-Z : High impedance, L : Low level (current sink) <2nd byte>
Data
Function
Setting
Bit D7 D6 D5 D4 D3 D2 D1 D0
Data 1 or 0 1 or 0
Function
Setting
ROTATION ENABLE
ch CCW/CW ch ON/OFF ch
Setting (1 to 255) t = 256 s
6-bit data input
Number of
Pulse Number
pulses in 1 VD Setting (0 to 63)
n = 4 pulses Note
Note Input other than "0".
Note The number of pulses can be varied in 4-pulse steps.
<3rd byte>
Bit D7 D6 D5 D4 D3 D2 D1 D0 8-bit data input Note First Point Magnetize Wait
Start point drive wait 256 s to 65.28 ms Setting (1 to 255) t = 256 s
<3rd byte>
Data Function Setting Bit D7 D6 D5 D4 D3 D2 D1 D0 Low-order 8-bit data input Data 15-bit data Function Setting
ch pulse
cycle
0.25 to 8191.75 s
Pulse Width
Setting (1 to 32767) t = 0.25 s
Note Input other than "0".
Data Sheet S15973EJ1V0DS
9
PD16835A
<4th byte>
Bit D7 D6 D5 D4 D3 D2 D1 D0 5-bit data input Chopping Frequency Data 1 or 0 0 0 Function OSCSEL Setting Internal/external Chopping frequency : 32 to 124 kHz Setting (8 to 31) f = 4 kHz
Note
<4th byte>
Bit D7 D6 D5 D4 D3 High-order D2 D1 D0 8-bit data input Data 1 or 0 15-bit data Function Current Set Setting set2/set1
ch
pulse cycle :
0.25 to 8191.75 s
Pulse Width
Setting (1 to 32767) t = 0.25 s
Note The frequency is 0 kHz if 0 to 7 is input. <5th byte>
Bit D7 D6 D5 D4 D3 D2 D1 D0 0 Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 Data EXT ENABLE
Note1
<5th byte>
EXT ENABLE
Note1
Bit D7 D6 D5 D4 D3 D2 D1 D0
Data 1 or 0 1 or 0
Function
Setting
ch CCW/CW ch ON/OFF
ROTATION ENABLE
ROTATION
Note2
ROTATION
Note2
Pulse Out FF7 FF3 Checksum Note3 Chopping Note4
Pulse Out FF7 FF3 FF2 FF1
ch
6-bit data input Number of
Pulse Number
pulses in 1 VD Setting (1 to 63)
n = 4 pulses Note
Notes 1. H level : Conducts, L level : Stops 2. H level : Reverse (CCW), L level : Forward (CW) 3. H level : Normal data input, L level : Abnormal data input 4. Not output in internal oscillation mode. 5. Select one of D0 to D6 and input "1". If two or more of D0 to D6 are selected, they are positively ORed for output. <6th byte>
Bit D7 D6 D5 D4 D3 D2 D1 D0 4-bit data input 4-bit data input Data Function Setting
ch Output current
Note The number of pulses can be varied in 4-pulse steps.
<6th byte>
Bit D7 D6 D5 D4 D3 D2 D1 D0 Low-order 8-bit data input Data 15-bit data Function Setting
ch
Current Set2
setting 2 EVR : 100
to 250 mV Setting (0 to 15) Note
ch pulse
cycle:
0.25 to 8191.75 s
ch Output current
Pulse Width
Setting (1 to 32767) t = 0.25 s
ch
Current Set1
setting 1 EVR : 100
to 250 mV Setting (0 to 15) Note
Note A voltage of about double EVR is output to the FIL pin.
10
Data Sheet S15973EJ1V0DS
PD16835A
<7th byte>
Bit D7 D6 D5 D4 D3 D2 D1 D0 4-bit data input 4-bit data input Data Function Setting
ch Output
<7th byte>
Bit D7 D6 D5 D4 D3 D2 D1 D0 High-order 7-bit data input Data 1 or 0 15-bit data Function Current Set Setting set2/set1
ch
Current Set2
current setting 2
EVR: 100 to 250 mV Setting (0 to 15)
Note
ch pulse
cycle:
0.25 to 8191.75 s
ch Output
Pulse Width
Setting (1 to 32767) t = 0.25 s
ch
Current Set1
current setting 1
EVR: 100 to 250 mV Setting (0 to 15)Note
Note A voltage of about double EVR is output to the FIL pin. <8th byte>
Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 Checksum Checksum Note Function Setting
<8th byte>
Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 Checksum Checksum Note Function Setting
Note Data is input so that the sum of the 1st through the 8th bytes is 00H.
Note Data is input so that the sum of the 1st through the 8th bytes is 00H.
Data Sheet S15973EJ1V0DS
11
PD16835A
Data Configuration Data can be input in either of two ways. Initial data can be input when the power is first applied, or standard data can be input during normal operation. Input serial data with the LSB first, i.e., starting from the D0 bit (LSB) of the 1st byte. Therefore, the D7 bit of the 8th byte is the most significant bit (MSB). When inputting initial data, set a start point wait time that specifies the delay from power application to pulse output, and the start point drive wait time. At the same time, also set a chopping frequency and a reference voltage (EVR) that determines the output current of each channel. Because the PD16835A has an EXT pin for monitoring the internal operations, the parameter to be monitored can be selected by initial data. When inputting standard data, input the rotation direction of each channel, the number of pulses, and the data for the pulse cycle. Initial data or standard data is selected by using bits D5 to D7 of the 1st byte (see Table 5-1). Table 5-1. Data Selection Mode (1st byte)
D7 1 0 D6 1 0 D5 1 0 Initial data Standard data Data type
Remark If the high-order three bits are high, the initial data is selected; if they are low, the standard data is selected. Data other than (0, 0, 0) and (1, 1, 1) must not be input. Input the serial data during start point wait time. Details of Data Configuration How to input initial data and standard data is described below. (1) Initial data input <1st byte> The 1st byte specifies the type of data (initial data or standard data) and determines the presence or absence of the EXP pin output. Bits D5 to D7 of this byte specify the type of data as shown in Table 5-1, while bits D0 to D3 select the EXP output (open drain). Table 5-2. 1st Byte Data Configuration
Bit Data D7 1 D6 1 D5 1 D4 0 D3 0 or 1 D2 0 or 1 D1 0 or 1 D0 0 or 1
The EXP pin goes low (current sink) when the input data is "0", and high (high impedance state) when the input data is "1". Pull this pin up to VDD for use. Input "0" to bit D4.
12
Data Sheet S15973EJ1V0DS
PD16835A
<2nd byte> The 2nd byte specifies the delay between data being read and data being output. This delay is called the start up wait time, and the motor can be driven from that point at which the start up wait time is "0". This time is counted at the rising edge of VD. The start up wait time can be set to 65.28 ms (when a 4-MHz clock is input), and can be fine-tuned by means of 8-bit division (256-s step: with 4-MHz clock). The start up wait time is set to 65.28 ms when all the bits of the 2nd byte are set to "1". Caution Always input data other than "0" to this byte because the start up wait time is necessary for latching data. If "0" is input to this byte, data cannot be updated. Transfer standard data during the start up wait time. <3rd byte> The 3rd byte specifies the delay between the start point wait time being cleared and the output pulse being generated. This time is called the start up drive wait time, and the output pulse is generated from the point at which the start up drive wait time reaches "0". The start up drive wait time is counted at the falling edge of the start up wait time. The start up drive wait time can be set to 65.28 ms (with 4-MHz clock) and can be fine-tuned by means of 8-bit division (256-s step: with 4-MHz clock). The start up drive wait time is set to 65.28 ms when all the bits of the 3rd byte are "1". Caution Always input data other than "0" to this byte because the start up drive wait time is necessary for latching data. If "0" is input to this byte, data cannot be updated. <4th byte> The 4th byte selects a chopping frequency by using 5-bit data. It also selects whether the chopping frequency is created by dividing the original oscillation (external clock) or whether the internal oscillator is used. The chopping frequency is selected by bits D0 to D4. Bit D7 specifies the method used to create the chopping frequency. When this bit is "0", the original oscillation (external clock input to OSCIN) is used; when it is "1", the internal oscillator is used. Bits D5 and D6 are fixed to "0". The chopping signal is output after the initial data has been input and the first standard data has been latched (see Timing Chart). Table 5-3. 4th Byte Data Configuration (Initial data)
Bit Data D7 0 or 1 D6 0 D5 0 D4 0 or 1 D3 0 or 1 D2 0 or 1 D1 0 or 1 D0 0 or 1
The chopping frequency is set to 0 kHz and to a value in the range of 32 to 124 kHz (in 4-kHz steps), as follows. Although the chopping frequency is set by 5 bits of data, it is internally configured using 7-bit data (with the loworder 2 bits fixed to 0).
Data Sheet S15973EJ1V0DS
13
PD16835A
Bit Data
D7 0 or 1
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0
fOSC = 0 kHz
Bit Data
D7 0 or 1
D6 0
D5 0
D4 0
D3 0
D2 1
D1 1
D0 1
fOSC = 0 kHz
Bit Data
D7 0 or 1
D6 0
D5 0
D4 0
D3 1
D2 0
D1 0
D0 0
fOSC = 32 kHz
Bit Data
D7 0 or 1
D6 0
D5 0
D4 0
D3 1
D2 0
D1 0
D0 1
fOSC = 36 kHz
Bit Data
D7 0 or 1
D6 0
D5 0
D4 1
D3 1
D2 1
D1 1
D0 1
fOSC = 124 kHz
<5th byte> The 5th byte selects a parameter to be output to the EXT pin (logic operation monitor pin). Input data to bits D0 to D6 of this byte. Bit D7 is fixed to "0". There are two EXT pins. EXT indicates the operating status of ch, and EXT indicates that of ch. The relationship between each bit and each EXT pin is as shown in Table 5-4. Table 5-4. 5th Byte Data Configuration (Initial data)
Bit D7 D6 D5 D4 D3 D2 D1 D0 Data 0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 EXT Not used ENABLE ROTATION PULSEOUT FF7 FF3 CHECKSUM CHOPPING EXT Not used ENABLE ROTATION PULSEOUT FF7 FF3 FF2 FF1
The checksum bit is cleared to "0" in the event of an error. Normally, it is "1". If two or more signals that output signals to EXT and EXT are selected, they are positively ORed for output. Caution The CHOPPING signal is not output in internal oscillation mode.
14
Data Sheet S15973EJ1V0DS
PD16835A
Remark The meanings of the symbols listed in Table 5-4 are as follows: ENABLE : Output setting (H : Conducts, L : Stops) ROTATION : Rotation direction (H : Reverse (CCW), L : Forward (CW)) PULSEOUT : Output pulse signal FF7 : Presence/absence of pulse in LATCH cycle (Outputs H level if output pulse information exists in standard data.) FF3 : Pulse gate (output while pulse exists) FF2 : Outputs H level during start up wait time + start up drive wait time FF1 : Outputs H level during start up wait time CHECKSUM : Checksum output (H : when normal data is transmitted, L : when abnormal data is transmitted) CHOPPING : Chopping wave output (in original oscillation mode only) <6th byte> The 6th byte sets the peak output current value of ch. The output current is determined by the EVR reference voltage. The 250-mV (TYP.) voltage input from an external source to the VREF pin is internally doubled and input to a 4-bit D/A converter. By dividing this voltage by 4-bit data, an EVR reference voltage can be set inside the IC within the range of 200 to 500 mV, in units of 20 mV. The PD16835A can set two values of the EVR reference voltage in advance. This is done by using bits D0 to D3 or D4 to D7. Which of the two EVR reference voltage values is to be used is specified by the CURRENT SET bit in the standard data. If all the bits of the 6th byte are "0", the EVR reference voltage of 200 mV is selected; if they are "1", the EVR reference voltage of 500 mV is selected. Table 5-5. 6th Byte Data Configuration (Initial data)
Bit Data D7 0 or 1 D6 0 or 1 D5 0 or 1 D4 0 or 1 D3 0 or 1 D2 0 or 1 D1 0 or 1 D0 0 or 1
Remark Bits D4 to D7 : Reference voltage 2 (EVR 2) Bits D0 to D3 : Reference voltage 1 (EVR 1) <7th byte> The 7th byte specifies the peak output current value of ch. The output current is determined by the EVR reference voltage. The 250-mV (TYP.) voltage input from an external source to the VREF pin is internally doubled and input to a 4-bit D/A converter. By dividing this voltage by 4-bit data, an EVR reference voltage can be set inside the IC within a range of 200 to 500 mV, in units of 20 mV. The PD16835A can set two values of the EVR reference voltage in advance. This is done using bits D0 to D3 or D4 to D7. Which of the two EVR reference voltage values is to be used is specified by the CURRENT SET bit in the standard data. If all the bits of the 7th byte are "0", the EVR reference voltage of 200 mV is selected; if they are "1", the EVR reference voltage of 500 mV is selected.
Data Sheet S15973EJ1V0DS
15
PD16835A
Table 5-6. 7th Byte Data Configuration (Initial data)
Bit Data D7 0 or 1 D6 0 or 1 D5 0 or 1 D4 0 or 1 D3 0 or 1 D2 0 or 1 D1 0 or 1 D0 0 or 1
Remark Bits D4 to D7 : Reference voltage 2 (EVR 2) Bits D0 to D3 : Reference voltage 1 (EVR 1) <8th byte> The 8th byte is checksum data. Normally, the sum of the 8-byte data is 00H. If the sum is not 00H because data transmission is abnormal, the stepping operation is inhibited and the checksum output pin (EXT pin) is kept "L".
(2) Standard data input <1st byte> The 1st byte specifies the type of data and whether the EXP pin output is used, such as when the initial data is input. Table 5-7. 1st Byte Data Configuration
Bit Data D7 1 D6 1 D5 1 D4 0 D3 0 or 1 D2 0 or 1 D1 0 or 1 D0 0 or 1
The EXP pin goes low (current sink) when the input data is "0", and high (high impedance state) when the input data is "1". Input "0" to bit D4. <2nd byte> The 2nd byte specifies the rotation direction of the channel, enables output of the channel, and the number of pulses (252 pulses MAX.) during the 1VD period (in 1 cycle of FF2) of the channel. Bit D7 is used to specify the rotation direction. The rotation is in the forward direction (CW mode) when this bit is "0"; it is in the reverse direction (CCW mode) when the bit is "1". Bit D6 is used to enable the output of the channel. The channel enters the high impedance state when this bit is "0"; it is in conduction mode when the bit is "1". The number of pulses is set by bits D0 to D5. It is set by 6 bits in terms of software. However, the actual circuit uses an 8-bit counter with the low-order two bits fixed to "0". Therefore, the number of pulses that is actually generated during start up wait time + start up drive wait (FF2) cycle is the number of pulses input x 4. The number of pulses can be set to a value in the range of 0 to 252, in units of 4 pulses.
16
Data Sheet S15973EJ1V0DS
PD16835A
Table 5-8. 2nd Byte Data Configuration (Standard data)
Bit Data D7 0 or 1 D6 0 or 1 D5 0 or 1 D4 0 or 1 D3 0 or 1 D2 0 or 1 D1 0 or 1 D0 0 or 1
Rotation direction <3rd and 4th bytes>
ENABLE
Number of pulses
The 3rd and 4th bytes select the pulse cycle of the channel and which of the two reference voltages, created in the initial mode, is to be used (CURRENT SET). The pulse cycle is specified using 15 bits : bits D0 (least significant bit) to D7 of the 3rd byte, and bits D0 to D6 (most significant bit) of the 4th byte. The pulse cycle can be set to a value in the range of 0.25 to 8191.75 s in units of 0.25 s (with a 4-MHz clock). CURRENT SET is specified by bit D7 of the 4th byte. When this bit is "0", reference voltage 1 (EVR1) is selected; when it is "1", reference voltage 2 (EVR2) is selected. For further information, refer to the description of the 6th byte of the initial data. Table 5-9. 4th Byte Data Configuration (Standard data)
Bit Data D7
0 or 1
Table 5-10. 3rd Byte Data Configuration (Standard data)
D7
0 or 1
D6
0 or 1
D5
0 or 1
D4
0 or 1
D3
0 or 1
D2
0 or 1
D1
0 or 1
D0
0 or 1
D6
0 or 1
D5
0 or 1
D4
0 or 1
D3
0 or 1
D2
0 or 1
D1
0 or 1
D0
0 or 1
CURRENT SET bit
Most significant
Least significant bit
(Reference) 6th Byte Data Configuration for Initial Data
Bit Data D7 0 or 1 D6 0 or 1 D5 0 or 1 D4 0 or 1 D3 0 or 1 D2 0 or 1 D1 0 or 1 D0 0 or 1
Remark Bits D4 to D7 : Reference voltage 2 (EVR 2) Bits D0 to D3 : Reference voltage 1 (EVR 1) <5th byte> The 5th byte specifies the rotation direction of the channel, enables output of the channel, and the number of pulses (252 pulses MAX.) during the 1VD period (in one cycle of FF2) of the channel. Bit D7 is used to specify the rotation direction. The rotation is in the forward direction (CW mode) when this bit is "0"; it is in the reverse direction (CCW mode) when the bit is "1". Bit D6 is used to enable the output of the channel. The channel goes into a high impedance state when this bit is "0"; it is in the conduction mode when the bit is "1". The number of pulses is set by bits D0 to D5. It is set by six bits in terms of software. However, the actual circuit uses an 8-bit decoder with the low-order two bits fixed to "0". Therefore, the number of pulses that is actually generated during start up wait time + start up drive wait (FF2) cycle is the number of pulses input x 4. The number of pulses can be set in a range of 0 to 252 and in units of 4 pulses.
Data Sheet S15973EJ1V0DS
17
PD16835A
Table 5-11. 5th Byte Data Configuration (Standard data)
Bit Data D7 0 or 1 D6 0 or 1 D5 0 or 1 D4 0 or 1 D3 0 or 1 D2 0 or 1 D1 0 or 1 D0 0 or 1
Rotation direction <6th and 7th bytes>
ENABLE
Number of pulses
The 6th and 7th bytes select the pulse cycle of the channel and which of the two reference voltages, created in the initial mode, is to be used (CURRENT SET). The pulse cycle is specified using 15 bits : bits D0 (least significant bit) to D7 of the 6th byte, and bits D0 to D6 (most significant bit) of the 7th byte. The pulse cycle can be set to a value in the range of 0.25 to 8191.75 s in units of 0.25 s (with a 4-MHz clock). CURRENT SET is specified by bit D7 of the 7th byte. When this bit is "0", reference voltage 1 (EVR1) is selected; when it is "1", reference voltage 2 (EVR2) is selected. For further information, refer to the description of the 7th byte of the initial data. Table 5-12. 7th Byte Data Configuration (Standard data)
Bit Data D7
0 or 1
Table 5-13. 6th Byte Data Configuration (Standard data)
D7
0 or 1
D6
0 or 1
D5
0 or 1
D4
0 or 1
D3
0 or 1
D2
0 or 1
D1
0 or 1
D0
0 or 1
D6
0 or 1
D5
0 or 1
D4
0 or 1
D3
0 or 1
D2
0 or 1
D1
0 or 1
D0
0 or 1
CURRENT SET
Most significant bit (Reference) 7th Byte Data Configuration for Initial Data
Bit Data D7 0 or 1 D6 0 or 1 D5 0 or 1 D4 0 or 1 D3 0 or 1 D2 0 or 1 D1 0 or 1 D0 0 or 1
Least significant bit
Remark Bits D4 to D7 : Reference voltage 2 (EVR 2) Bits D0 to D3 : Reference voltage 1 (EVR 1) <8th byte> The 8th byte is checksum data. Normally, the sum of the 8-byte data is 00H. If the sum is not 00H because data transmission is abnormal, the stepping operation is inhibited and the checksum output pin (EXT pin) is held at "L".
18
Data Sheet S15973EJ1V0DS
PD16835A
(Data Update Timing) The standard data (pulse width, number of pulses, rotation direction, current setting, and ENABLE) of this product are set and updated at the following latch timing. Table 5-14. Data Update Timing
ENABLE change Pulse width Number of pulses Rotation direction Current setting ENABLE 11 FF2 FF2 FF2 FF2 FF2 01 FF2 FF2 FF2 FF1 FF1 10 FF2 FF2 FF2 FF2 FF2 00 - - - - -
The timing at which data is to be updated differs, as shown in Table 5-14, depending on the enabled status. For example, suppose the enable signal is currently "0" (output high impedance) and "1" (output conduction) is input by the next data. In this case, the pulse width, number of pulses, and rotation direction signals are updated at FF2(upon the completion of start up wait), and the current setting and ENABLE signals are updated at FF1 (upon completion of start up drive wait).
VD
FF1 Start up wait FF2 Start up wait + start up drive wait
Pulse output
Pulse width, number of pulses, and rotation direction are updated. Current setting and ENABLE are updated (ENABLE change: 0 to 1).
VD (1) LATCH I1 S1 (2) S2 (3) S3
Initial data identification
Standard data identification
I1 data is output. FF1, FF2 output
Data Sheet S15973EJ1V0DS
19
PD16835A
(1) Pulse width Internal data retained. Output reset Rotation direction Number of pulses Internal output retained Internal data retained. Output reset Current setting ENABLE Internal output retained Internal output retained
(2) Not output
(3) Updated to S2 data at FF2
Not output Not output
Not output Not output
Updated to S2 data at either FF1 or FF2 by enable data of (2)
The initial mode of this product is as follows. The IC operation can be initialized as follows: (1) Turns ON VDD. (2) Make RESET input "L". (3) Input serial initial data. In initial mode, the operating status of the IC is as shown in Table 5-15. Table 5-15. Operations in Initial Mode
Item Current consumption OSC 100 A Oscillation stops. Input of external clock is inhibited. VD FF1 to FF7 PULSE OUT EXP0 to EXP3 Input inhibited. "L" level "L" level Undefined in the case of (1) above. Previous value is retained in the case of (2) above. Can be updated by serial data in the case of (3) above. Serial operation Can be accessed after initialization in the case of (1) above. Can be accessed after RESET has gone "H" in the case of (2) above. Can be accessed in the case of (3) above. Specifications
Step pulse output is inhibited and FF7 is made "L" if the following conditions are satisfied. (1) If the set number of pulses (2nd/5th: standard data) is 00H. (2) If the checksum value is other than 00H. (3) If the start up wait time is set to 1 VD or longer. (4) If the start up wait time + start up drive wait time is set to 1 VD or longer. (5) If start up wait is completed earlier than LATCH (). (6) If VD is not input.
20
Data Sheet S15973EJ1V0DS
PD16835A
Cautions on Correct Use (1) With this product, input the data for start up wait and start up drive wait. Because the standard data are set or updated by these wait times, if the start up wait time and start up drive wait time are not input, the data are not updated. (2) The start up wait time must be longer than LATCH. (3) If the rising of the start up drive wait time is the same as the falling of the last output pulse, a count error occurs, and the IC may malfunction. (4) Input the initial data in a manner that it does not straddle the video sync signal (VD). If it does, the initial data is not latched. (5) Transmit the standard data during the start up wait time (FF1). If it is input at any other time, the data may not be transmitted correctly. (6) If the LGND potential is undefined, the data may not be input correctly. Keep the LGND potential to the minimum level. It is recommended that LGND and PGND be divided for connection (single ground) to prevent the leakage of noise from the output circuit.
Data Sheet S15973EJ1V0DS
21
PD16835A
6. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Input voltage Reference voltage H bridge drive current Note 1 Instantaneous H bridge drive current Note 1 Power consumption Note 2 Peak junction temperature Storage temperature PT TCH(MAX.) Tstg 1.0 150 -55 to +150 W C C VDD VM VIN VREF IM(DC) IM(pulse) DC PW 10 ms, Duty 5% Symbol Condition Rating -0.5 to +6.0 -0.5 to +11.2 -0.5 to VDD+ 0.5 500 150 300 Unit V V V mV mA/phase mA/phase
Notes 1. Permissible current per phase with the IC mounted on a PCB. 2. When the IC is mounted on a glass epoxy PCB (10 cm x 10 cm x 1 mm). Caution If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings. Recommended Operating Range
Parameter Supply voltage Input voltage Reference voltage EXP pin input voltage EXP pin input current H bridge drive current H bridge drive current Clock frequency (OSCIN) Clock frequency amplitude Serial clock frequency (SCLK) Video sync signal width LATCH signal wait time SCLK wait time SDATA setup time SDATA hold time Chopping frequency Reset signal pulse width Operating temperature Peak junction temperature VDD VM VIN VREF VEXPIN IEXPIN IM(DC) IM(pulse)
Note 1
Symbol
MIN. 2.7 4.8 0 225
TYP.
MAX. 5.5 11 VDD
Unit V V V mV V
250
275 VDD 100
A
mA mA MHz V MHz ns ns ns ns ns
-100 -200 3.9 0.7 VDD 4
+100 +200 4.2 VDD 5.0
fCLK Note 2 VfCLK Note 2 fSCLK PW(VD) Note 3 t(VD-LATCH) Note 4 t(SCLK-LATCH) tsetup Note 4 thold Note 4 fOSC tRST TA TCH(MAX.)
Note 3 Note 4
250 400 400 80 80 32 100 -10 +70 125 124
kHz
s
C C
Notes 1. PW 10 ms, duty 5% 2. COSC = 33 pF, VREF = 250 mV 3. fCLK = 4 MHz 4. Serial data delay time(see the figure on the next page.)
22
Data Sheet S15973EJ1V0DS
PD16835A
VD t (VD-LATCH) LATCH
64 clocks (8 bits x 8 bytes)
SCLK t (SCLK-LATCH) t (SCLK-LATCH)
Ignored because LATCH is at L level.
Ignored because LATCH is at L level.
LATCH
50%
SDATA
D1 50% 50%
D2
D3
SCLK
t (SCLK-LATCH)
tsetup thold
Data Sheet S15973EJ1V0DS
23
PD16835A
ELECTRICAL CHARACTERISTICS DC Characteristics (Unless otherwise specified, VDD = 3.3 V, VM = 6.0 V, VREF = 250 mV, TA = 25C, fCLK = 4 MHz, COSC = 33 pF, CFIL = 1000 pF, EVR = 100 mV (0000))
Parameter Off VM pin current VDD pin current VDD pin current High level input voltage Low level input voltage Input hysteresis voltage Monitor output voltage 1 (EXT , ) Monitor output voltage 2 (EXP0 to EXP3 : open drain) High level input current Low level input current Reset pin high level input current Reset pin low level input current Input pull down resistor H bridge ON resistance
Note 1
Symbol IMO(RESET) IDD IDD(RESET) VIH VIL VH VOM (H), VOM (H) 5th byte VOM (L), VOM (L) VOEXP(H) VOEXP(L) IIH IIL IIH(RST) 5th byte Pull up (VDD)
Condition No load, reset period Output open Reset period LATCH, SCLK, SDATA, VD, RESET, OSCIN
MIN.
TYP.
MAX. 1.0 3.0 100
Unit
A
mA
A
V
0.7 VDD 0.3 VDD 300 0.9 VDD 0.1 VDD VDD 0.1 VDD 0.06 -1.0 1.0 -1.0
V mV V V V V mA
IOEXP = 100 A VIN = VDD VIN = 0 V VRST = VDD
A A A
200 3.5 0 5.0 k kHz 150 kHz 250 ns mA
IIL(RST)
VRST = 0
RIND RON fOSC(1) fOSC(2) fSTEP tVD IM
LATCH, SCLK, SDATA, VD IM = 100 mA DATA: 00000 (4th byte) DATA: 11111 (4th byte) Minimum step
50
Chopping frequency (internal oscillation: COSC = 100 pF) Step frequency VD delay time Note 2 Sine wave peak output current Note 3
100
124 4
L = 25 mH/R = 100 (1 kHz) EVR = 200 mV (1010) RS = 6.8 , fOSC = 64 kHz
52
FIL pin voltage Note 4 FIL pin step voltage
Note 4
VEVR VEVRSTEP
EVR = 200 mV (1010) Minimum step
370
400 20
430
mV mV
AC Characteristics (Unless otherwise specified, VDD = 3.3 V, VM = 6.0 V, TA = 25C, fCLK = 4 MHz)
Parameter H bridge output circuit turn on tONH time H bridge output circuit turn off tOFFH time IM = 100 mA Note 5 1.0 2.0 Symbol Condition IM = 100 mA Note 5 MIN. TYP. 1.0 MAX. 2.0 Unit
s s
Notes 1. Total of ON resistance at top and bottom of output H bridge 2. By OSCIN and VD sync circuit 3. FB pin is monitored. 4. FIL pin is monitored. A voltage about twice that of the EVR value is output to the FIL pin. 5. 10 to 90% of the pulse peak value without filter capacitor (CFIL)
24
Data Sheet S15973EJ1V0DS
TIMING CHART (1)
Initialization RESET VD LATCH Initial DATA I1 EXP: 1 OSCOUT (original oscillation) Start point wait (FF1) Start point wait + start point drive wait (FF2) ENABLE OUTNote 1 Chopping pulse EXP0 to EXP3 PULSE OUT PULSE GATE (FF3) PULSE CHECKNote 2 (FF7) CHECK SUMNote 3 Output by chopping setting of I1 data Output by EXP setting of I1 data Output by EXP setting of S1 data S2DATA output Outputs high level while pulse is being generated Outputs high level for standard data while a pulse output signal exists (LATCH cycle) High level because data is normal. Low level because data is abnormal. No pulse output because data is erroneous Restore to high level because data is normal. Output by EXP setting of S2DATA S4DATA output Pulse error Input at rising edge of RESET Output by I1 data Output by I1 data Output by S2 data setting Output by S5 data setting Standard Dummy data S1 EXP :0 ENABLE: 0 Standard :1 S2 EXP ENABLE: 1 Standard S3 EXP : 1 error DATA Standard :0 S4 EXP ENABLE: 1 Standard S5 EXP :1 ENABLE: 0
Data Sheet S15973EJ1V0DS
Enable
SCLK SDATA 8th byte
Notes 1. ENABLE is set at the falling edge of FF1 when the level changes from low to high, and at the falling edge of FF2 when the level changes from high to low.
D0 D1 D2 D3 D4 D5 D6 D7
PD16835A
1st byte
2. FF7 is an output signal that is used to check for the presence or absence of a pulse in the standard data, is updated at the falling edge of LATCH and reset once at the rising edge of LATCH. If CHECK SUM is other than "00H", FF7 goes low, inhibiting pulse output, even if a pulse is generated. 3. CHECK SUM output is updated at the falling edge of LATCH.
(LSB) Data is held at rising edge of SCLK.
25
PD16835A
TIMING CHART (2)
CLK (PULSE OUT)
MOB
(CW mode) Current direction: A2 H bridge , 1ch output status Current direction: A1 A2 A1
Current direction: B2 H bridge , 2ch output status
B1
Current direction: B2
B1
Current direction: B1
B2
(Expanded view)
Note1 Note2 Note1
CW mode CLK PULSE OUT Position No. 1 2 3 4 5 6 5
CCW mode
CW mode
4
3
2
3 CCW
4
H bridge 1ch output status
CW CW CCW
CW CW
H bridge 2ch output status
CCW CW CW
CCW
Notes1. In CW mode : Position No. is incremented. 2. In CCW mode : Position No. is decremented.
Remarks 1. The current value of the actual wave is approximated to the value shown on the next page. 2. The C1, C2, D1, and D2 pins of channel correspond to the A1, A2, B1, and B2 pins of channel. 3. The CW mode is set if the D7 bit of the 2nd and 5th bytes of the standard data is "0". 4. The CCW mode is set if the D7 bit of the 2nd and 5th bytes of the standard data is "1".
26
Data Sheet S15973EJ1V0DS
PD16835A
RELATION BETWEEN ROTATION ANGLE, PHASE CURRENT, AND VECTOR QUANTITY (64-DIVISION MICRO STEP) (Values of PD16835A for reference)
Step Rotation angle ( ) MIN. - 2.5 12.4 22.1 31.3 40.1 48.6 58.4 65.7 72.3 78.1 83.2 87.4 90.7 93.2 - - A phase current TYP. 0 9.8 19.5 29.1 38.3 47.1 55.6 63.4 70.7 77.3 83.1 88.2 92.4 95.7 98.1 100 100 MAX. - 17.0 26.5 36.1 45.3 54.1 62.6 68.4 75.7 82.3 88.1 93.2 97.4 100.7 103 - - MIN. - - 93.2 90.7 87.4 83.2 78.1 72.3 65.7 58.4 48.6 40.1 31.3 22.1 12.4 2.5 - B phase current TYP. 100 100 98.1 95.7 92.4 88.2 83.1 77.3 70.7 63.4 55.6 47.1 38.3 29.1 19.5 9.8 0 MAX. - - 103 100.7 97.4 93.2 88.1 82.3 75.7 68.4 62.6 54.1 45.3 36.1 26.5 17.0 - Vector quantity TYP. 100 100.48 100 100.02 100.02 99.99 99.98 99.97 99.98 99.97 99.98 99.99 100.02 100.02 100 100.48 100
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0 5.6 11.3 16.9 22.5 28.1 33.8 39.4 45 50.6 56.3 61.9 67.5 73.1 78.8 84.4 90
Remark These data do not indicate guaranteed values.
Data Sheet S15973EJ1V0DS
27
PD16835A
7. PACKAGE DRAWING
38-PIN PLASTIC SSOP (7.62 mm (300))
38 20 detail of lead end F G
1 A
19 E
P
L
H I S J
C D M
M
N
S
B K
NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D E F G H I J K L M N P
MILLIMETERS 12.70.3 0.65 MAX. 0.65 (T.P.) 0.37 +0.05 -0.1 0.1250.075 1.6750.125 1.55 7.70.2 5.60.2 1.050.2 0.2 +0.1 -0.05 0.60.2 0.10 0.10 +7 3 -3 P38GS-65-BGG-1
28
Data Sheet S15973EJ1V0DS
PD16835A
8. RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E). Type of Surface Mount Device
PD16835AGS-BGG: 38-pin plastic shrink SOP (7.62 mm (300))
Process Infrared Ray Reflow Soldering conditions Peak temperature: 235C or below (Package surface temperature), Reflow time: 30 seconds or less (at 210C or higher), Maximum number of reflow processes: 3 time or less, Number of days: None Note, Flux: Rosin-based flux with low chlorine content (chlorine 0.2 Wt% or below) is recommended. Vapor Phase Soldering Peak temperature: 215C or below (Package surface temperature), Reflow time: 40 seconds or less (at 200C or higher), Maximum number of reflow processes: 3 time or less, Number of days: None Note, Flux: Rosin-based flux with low chlorine content (chlorine 0.2 Wt% or below) is recommended. Wave Soldering Solder temperature: 260C or below, Flow time: 10 seconds or less, Maximum number of flow processes: 1 time, Pre-heating temperature: 120C or below (Package surface temperature), Flux: Rosin-based flux with low chlorine content (chlorine 0.2 Wt% or below) is recommended. Partial Heating Method Pin temperature: 300C or below, Heat time: 3 seconds or less (Per each side of the device). - WS60-00-1 VP15-00-3 Symbol IR35-00-3
Note Number of days the device can be stored after the dry pack has been opened, at conditions of 25C, 65%RH. Caution Apply only one kind of soldering condition to a device, except for "partial heating method", or the device will be damaged by heat stress.
Data Sheet S15973EJ1V0DS
29
PD16835A
[MEMO]
30
Data Sheet S15973EJ1V0DS
PD16835A
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S15973EJ1V0DS
31
PD16835A
* The information in this document is current as of January, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
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